Skill development programme on FPGA based System Design

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Salient Features

  • 55% to 60% Practical and 45% to 40% Theory Session as per the course curriculum
  • Tutorials (personal attention) & Lectures, assisted with models and multimedia aids
  • Interactive Sessions on Real-time problems and participant may discuss their own application
  • Hands-on Practical exposure
  • Invited Lectures from Professionals/Industrial experts

Lab Trainers and Faculty

  • Experts in the field
  • Relevant long term R&D/Industry Experienced
  • Executed high level R&D projects
  • Expert facilitators and training professionals

Team Members

  • Dr. Kota Solomon Raju, Senior Principal Scientist
  • Dr. Ravi Saini, Senior Scientist
  • Dr. Jai Gopal Pandey, Senior Scientist
  • Mr.Pramod Kumar Tanwar, Senior Scientist
  • Dr. Sanjay Singh, Scientist
  • Mr. Gaurav Purohit, Scientist
  • Mr.Sumeet, Scientist

Important Details

Last Date for Registration: 02.06.2019
Last Date of Payment: 03.06.2019
Date of commencement: 03.06.2019
Duration: 160 Hours (One Month) ; 03rd  June 2019 to 02nd July 2019 (Monday to Friday 10 AM to 5 PM)
Qualification: Industry Professionals/Faculties for Career enhancement & B.E. /B.Tech. (B.E. B.Tech. Final year students are also eligible)
Course Fee:

  • Rs. 40,000/- (Fourty Thousand rupees only) for Sponsored Candidates
  • Rs. 20,000/- (Twenty Thousand rupees only) for the students (B.E., M.E., Ph.D.)
  • Rs. 25,000/- (Twenty five Thousand rupees only) for academic faculty

Payment Details: Online or Demand Draft in favor of “Director, CEERI” payable at Pilani
Account No: 61033385318
Account Type: Savings
Bank Name: SBI, CEERI – Campus, Pilani
MICR No: 333003398
IFSC: SBIN0031398
RTGS: SBIN0031398
No. of Seats: 40 (First come First basis); Minimum 10 candidates required to start the course

Application Form

Attachments