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VERSION:2.0
PRODID:-//CSIR-CEERI, Pilani - EN - ECPv5.16.4//NONSGML v1.0//EN
CALSCALE:GREGORIAN
METHOD:PUBLISH
X-WR-CALNAME:CSIR-CEERI, Pilani - EN
X-ORIGINAL-URL:https://www.ceeri.res.in
X-WR-CALDESC:Events for CSIR-CEERI, Pilani - EN
BEGIN:VTIMEZONE
TZID:Asia/Kolkata
BEGIN:STANDARD
TZOFFSETFROM:+0530
TZOFFSETTO:+0530
TZNAME:IST
DTSTART:20190101T000000
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BEGIN:VEVENT
DTSTART;TZID=Asia/Kolkata:20190603T100000
DTEND;TZID=Asia/Kolkata:20190702T170000
DTSTAMP:20260609T013921
CREATED:20190416T121813Z
LAST-MODIFIED:20190515T120130Z
UID:9022-1559556000-1562086800@www.ceeri.res.in
SUMMARY:Skill development programme on FPGA based System Design
DESCRIPTION:Salient Features\n55% to 60% Practical and 45% to 40% Theory Session as per the course curriculum\nTutorials (personal attention) & Lectures\, assisted with models and multimedia aids\nInteractive Sessions on Real-time problems and participant may discuss their own application\nHands-on Practical exposure\nInvited Lectures from Professionals/Industrial experts\n\nLab Trainers and Faculty\nExperts in the field\nRelevant long term R&D/Industry Experienced\nExecuted high level R&D projects\nExpert facilitators and training professionals\n\nTeam Members\nDr. Kota Solomon Raju\, Senior Principal Scientist\nDr. Ravi Saini\, Senior Scientist\nDr. Jai Gopal Pandey\, Senior Scientist\nMr.Pramod Kumar Tanwar\, Senior Scientist\nDr. Sanjay Singh\, Scientist\nMr. Gaurav Purohit\, Scientist\nMr.Sumeet\, Scientist\n\nImportant DetailsLast Date for Registration: 02.06.2019\nLast Date of Payment: 03.06.2019\nDate of commencement: 03.06.2019\nDuration: 160 Hours (One Month) ; 03rd  June 2019 to 02nd July 2019 (Monday to Friday 10 AM to 5 PM)\nQualification: Industry Professionals/Faculties for Career enhancement & B.E. /B.Tech. (B.E. B.Tech. Final year students are also eligible)\nCourse Fee: \n\nRs. 40\,000/- (Fourty Thousand rupees only) for Sponsored Candidates\nRs. 20\,000/- (Twenty Thousand rupees only) for the students (B.E.\, M.E.\, Ph.D.)\nRs. 25\,000/- (Twenty five Thousand rupees only) for academic faculty\n\nPayment Details: Online or Demand Draft in favor of “Director\, CEERI” payable at Pilani\nAccount No: 61033385318\nAccount Type: Savings\nBank Name: SBI\, CEERI – Campus\, Pilani\nMICR No: 333003398\nIFSC: SBIN0031398\nRTGS: SBIN0031398\nNo. of Seats: 40 (First come First basis); Minimum 10 candidates required to start the course \nApplication FormClick here to fill the application form.\n\nAttachmentsSkill development programme on FPGA based System Design
URL:https://www.ceeri.res.in/event/skill-development-programme-on-fpga-based-system-design/
LOCATION:CSIR-CEERI\, Pilani\, Central Electronics Engineering Research Institute\, Pilani\, 333031\, India
ATTACH;FMTTYPE=image/jpeg:https://www.ceeri.res.in/wp-content/uploads/2019/04/FPGA_Image.jpg
ORGANIZER;CN="Dr.%20Kota%20Solomon%20Raju":MAILTO:solomon@ceeri.res.in, sdpceeri@gmail.com
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