Dr. Kota Solomon Raju

Senior Principal Scientist

Work Email: solomon@ceeri.res.in
Personal Email: kotasolomonraju@gmail.com
Mobile: 9460842188
EPBX Office: 2445
EPBX Residential: 2475
BSNL Office:
BSNL Residential:
BSNL Private:


Dr. Kota Soloman Raju is working as Sr. Principal Scientist in Societal Electronics Group(SAG), CSIR -Central Electronics Research Institute (CSIR – CEERI), Pilani, Rajasthan, India, and Professor, Academy of Scientific and Innovative Research (AcSIR), Hq: Ghaziabad . He Joined in CSIR-CEERI on 29 January 1998 as Scientist-B. He has been working in the field of an Advanced Embedded Electronic Systems Engineering for Information and Communication Technological applications and allied sciences & engineering. So far, as a PI, he proposed, defended and implemented 10 R&D projects out of which, some of them are multi-institutional projects, sponsored by various agencies including, Department of electronics and information technology (DeitY), MeitY, DST, and CSIR, S&T ministry, Government of India. Apart from the R&D assignments, He has been involved academic activities in various institutes like AcSIR, BITS, Hiroshima University (Japan) etc. From April 2017, he is a coordinator /head of Skill Development Programmes as part of “Skill India” mission of the Government of India through CSIR’s Integrated Skill Initiative program.

As a trusted R&D scientist, he can take-up challenging tasks to lead a premier R&D institute. This challenging task possess, a requirement of longstanding amicable, interactable leadership in the relevant technology with in-depth expertise to lay the foundation to achieve the objectives of institute vision and goals. He would like to take up this challenge in the field of
Electronics, Information, Communication & allied Sciences and Technologies to shape and nurture the country’s premier institute’s functional procedures to meet the future technological requirements of the country, while maintaining sustainability, ruggedness and good green environment by empowering individuals, societies in the country.

Areas of Interest:

  • Frameworks & System design for real-time diagnosis and prognosis of structural health monitoring (SHM); Data Driven models development; Using Hybrid model of AI /ML/DL and conventional methods;
  • Computing systems engineering for various applications (Cyber Physical Systems and Security, Internet of Things (IoT), Artificial Neural Network /Machine Learning /Deep Learning / Data Science algorithms, Communication (5G/beyond 5G etc.), WSN, Industry 4.0, Automation, Robotics, Signal, Image, video and audio processing)
  • Real-time Embedded and High Performance Reconfigurable Computing Systems (RCS /RASIP /Reconfigurable Embedded Computing Systems (RECS) /SOC/Embedded /ASIP Systems): System Design, System Architecture Optimization, Mapping & Scheduling and customization: Techniques– HW-SW Co-design; run-time partial reconfiguration; with realtime operating system support (using latest and advanced SOCs like MSP 430/432, ARM, RFSoCs like CC2652R, CC1352R, Multiprocessors and FPGAs like Zynq, Zynq Ultrascale+RFSoC),
    Real-time operating Systems (VxWorks, QNX) and Operating Systems for ESD (Tigen, Peta Linux, RIOT, Contiki, TinyOS, Free RTOS, etc.)
  • 5G and beyond wireless communication systems and concepts usage: WSN based systems design, Energy efficient routing and MAC algorithms for IEEE 802.15.4, Communication Protocols stack, including physical layer, Digital/Wireless /Mobile Communications

R&D Projects (More details given in “Appendix-Projects”): 02 Executing + 10 Completed as PI

Making project proposals, defending and presenting proposed project in the selection panel, project execution and lead the team to deliver the project objectives as per the schedule of the project is my major role.

  • Number of Current Projects as Principal Investigator: 02; Details of the projects as follows:
  1. (June 2019-June 2022) Structure Health Assessment and Rehabilitation Framework based on Cyber Physical System (Rs. 70.00 Lakhs; Minutes OM No: DST/ICPS/PAMC/Cluster (CPSR)/2018 dated 13th March 2018 and Sanction OM: DST/ICPS/Cluster (Cyber Physical Systems)/2018(G) dated 13th March 2019))
  2. (February 2019-March 2020) Skill Development Program under CSIR Integrated Skill Initiative, Skill India (Rs. 95.61 Lakhs; OM No: DGTC/SD/2019 dated 25th February 2019))
  • Number of projects completed successfully as Principal Investigator: 10; The projects are based on FPGAs (Zynq, Virtex-4, Virtex-5, Sparton-6) /ARM /SoC (Davinci-TM6446), MSP 430, CC2520, CC2530/38, CC2652R, CC1352R etc. Research area includes, ASIP, RASIP, Reconfigurable SDR, RCS, SHM using WSN, IoT etc. System design from system specification-to prototype implementation
  • Number of projects completed successfully as a team member: 04; The projects are based on PROFIBUS standard transceiver design, Profibus protocol stack design for DP, Signal Conditioning circuit for Pressure sensors, ASIP for Text to Speech Synthesizer using Klatt’s C-code

Professional Affiliations

  1. Coordinator and Head: Skill Development Programs, CSIR-CEERI under CSIR Integrated Skill Initiative, Skill India
  2. MoU with HU, Japan: Established MoU between CSIR-CEERI, Pilani and Hiroshima University (HU) Japan for international exchange programme; Coordinator for Joint research project and Sakura Youth Exchange programme
  3. Visiting Professor: Hiroshima University (Japan), BITS Pilani
  4. Regular member (2018-2020 for 3years); Co-opted member (2015-2017 for 3 years) G-4 Committee: Mechanization & Instrumentation, Indian Roads Congress, Ministry of Road Transport & Highways, Govt. of India
  5. Selection committee member for Young Scientist of the M.P. State
  6. Publication Chair and Co-convener for ICAES-2013
  7. Secretary, CEERI Educational Society (CES), Pilani
  8. Persistent effort for M.Tech. (Advanced Electronic Systems) course: Initiated M.Tech (Advanced Electronic Systems) course proposal and involved in main structure of courses syllabi
  9. Identifying and clearing the un-used dumping space to establish M.Tech. (AES) lab: Established (Advanced Electronic Systems) lab for AcSIR M.Tech
  10. Member of Board of Studies: R. V. College of Engineering, Bangalore, YMCA University Science and Technology, Faridabad
  11. Keynote speaker / Guest of Honor for conferences (IC and NC) – Appendix-Inv.
  12. Member for the foreign science and technology exposure tour (Europe, specifically Germany) by DST, Government of India (25th May – 2nd June 2013)
  13. Theses examiner (PhD and M.Tech./M.S./M.E.)
  14. Reviewer for Journal & Conferences
  15. Fellow (F-118694-5): The Institution of Engineers (India), New Delhi
  16. Life member: IETE, ACCS, ISOI; IEEE Member
  17. Involved as Chairman / Member in the Institute committees (CSIR-CEERI)


  • 98-Invited talks – 19 (IC) + 28 (NC) + 51 (National workshops /special programmes) -Appendix-Inv.
  • 01-(Filed) Patents; 43 – Journals; -Appendix-JP
  • 07- Book Chapters; 81 – Conferences – 35 IEEE + 15 ACM /Springer /URSI/Procedia Computer Science (Elsevier) + 15
  • Others (IC) + 16 Others (NC/ Symposium/ Seminar)


  • HW: Hands on experience with FPGA boards (Adaptive Compute Acceleration Platform (ACAP), Zynq UltraScale+ RFSoC ZCU111, Zynq UltraScale+ MPSoC ZCU102/104, Zynq-7000 SoC ZC702, ML 410/510/507/405/403 and Spartan6) Xilinx, SDR (with DM 6446 + V-4 SX devices) from Lyrtech, Warp Boards (V2 and V3) from Mango communications and DN8000K PCI (3FPGAs board), TI MSP430, CC2520, CC2530, CC2538, ARM versatile express boards, National Instruments (NI), NI PXI system for Zigbee signal generation and analysis, PXIe 5645R Vector Signal Transceiver and LabVIEW, High performance Logic Analyzer with FPGA debugging facility
  • SW: Using C, C++, EmbeddedC, VHDL, SystemC, Python, TCL /TK, Python and Shell scripting & HTML programming, and working knowledge in MATLAB Simulink, Xilinx Design tools (Vivado, ISE, EDK, PlanAhead, System Generator, ChipScope), Wind River Workbench, Tanner (T-Spice, S-Edit and L-Edit), Synopsis Compiler-II, Mentor graphics Modelsim, IAR IDE etc.
  • Systems: Practical experience on design and implementation of ASIP for speech synthesis and RASIP for Software-Defined Radio (SDR) architecture and its instruction set. Design of RCS with OS support with mapping and scheduling algorithms, Porting of RTOS (VxWorks, QNX) and OS (Linux, Peta Linux) on PPC 405 (V-4 FX) and PPC 440 (V-5 FXT). Digital baseband modules of GSM 1800, CDMA-IS 95, GPS receiver, IEEE 802.15.4, Zigbee, physical layer, Zigbee and PROFIBUS protocol stack
  • Protocols: Working knowledge on IoTivity framework, IEEE 802.15.4., Zigbee, Physical layer digital baseband modules for GSM as well as CDMA-IS 95, TCP/IP, WLAN and BLUETOOTH protocol standards, and UART, SPI, I2C, FMC, PMC, XMC, PCI, PCIe, HDMI, VGA interface standards

Number of Dissertation / Theses Guided

  • Doctor of Philosophy (Ph.D.) : 07 Awarded + 07 Ongoing
  • Master of Technology / Master of Engineering : 78
  • B.Tech. /B.E. : 30 (Even more guided but details not completely maintained)


  • Selected as Best Paper -02

Teaching Experience

  • Professor (Dual Designation) in Academy of Scientific and Innovative Research (AcSIR), Ghaziabad. AcSIR established by an Act of Parliament, Government of India. (The Gazette of India No.15 dated February 7, 2012 and notified on April 3, 2012) like Indian Institute of Technology (IIT) and other Institutions of National Importance. Headquarters: AcSIR, CSIR-HRDC Campus, Postal Staff College Area, Sector 19, Kamla Nehru Nagar, Ghaziabad, Uttar Pradesh- 201002; E-mail: info@acsir.res.in
  • Taught: At AcSIR, IIIT-Kota; BITS, Pilani; BKBIET, Pilani; JNU, Jaipur and NBKRIST, Nellore and other institutes; as a Visiting Professor


  • Doctor of Philosophy, 2004-2008; Department of Electronics and Computer Engineering, Indian Institute of Technology Roorkee, Roorkee – 247667, Uttarakhand, India. (Degree Awarded Date (DAD): 15th October 2008);
    Thesis Title: System Level Architecture and Optimal Mapping of Reconfigurable Computing
  • Master of Engineering, 2001-2003; Micro Electronics & VLSI Design, Birla Institute of Technology and Science (BITS) Pilani, Pilani-333031, Rajasthan, India. (DAD: 29th May 2003);
  • Bachelor of Engineering, 1994-1997; Electronics and Communication Engineering, SRKR Engineering College, Bhimavaram-534204, (Affiliated to Andhra University), Andhra Pradesh, India. (DAD: 13th March 1997);
  • Diploma in Electronics and Communication Engineering, 1989-1993; Electronics and Communication Engineering, Dr. B R Ambedkar Government Model Residential Polytechnic (Formerly, Government Model Residential Polytechnic), Bommuru, Rajahmundry-533124, Andhra Pradesh India. (DAD: 31st July 1993);

Website: Google Scholar Link