The objective of the activity was to design and develop an indigenous system-on-chip (SOC) processor towards the miniaturisation of autopilot hardware of Micro Aerial Vehicle for CSIR-NAL with the goal of achieving reduced weight and power consumption. The development of the SOC is based on available open-source IP cores and is to be fabricated through Multi-Project Wafer (MPW) facility. The detailed architecture design and the configuration of the final version of the SOC based on SPARCV8/Leon3 at the RTL level have been completed, along with the functional simulation. A test program that checks the integer pipeline, v8 Mul/Div, Timers, GPIO and Interrupt controller is executed during the simulation for verifying whether the design is rightly configured. Porting of the design to UMC 180 nm technology has been achieved. Memory generator for UMC 180 nm has been setup and required simulation and synthesis models have been integrated. Simulation of entire design ported to the Faraday Library along with memory and PLL has been achieved. The logic synthesis has been completed and the physical implementation is underway. The debugging and programming interface of the proposed SOC Platform using USB-to-Serial FTDI chip have been completed. Parallel NOR flash based ROM interface for the proposed SOC is currently being tested using a standard microcontroller. The packaging (PGA144) and pin position layout have been finalised. Software development (driver/toolchain etc. ) is underway. The MPW fabrication of the processor is planned for December 2016.
