This project is a multi-institutional Cluster project for the development of system-on-chip (SOC) Platform for secure speech communication involving CSIR-CEERI, IIT Jodhpur, NITKurukshetra, NIT-Hamirpur, ABV-IIITM Gwalior and TU-Patiala. It is part of DeitY/MCIT sponsored Special Manpower Development Programme for VLSI Design and Related Software for Chips-to-System Design (SMDP-C2SD). CSIR-CEERI is the Programme Coordinating Institute that covers 60 Institutes and Universities. In this project, a system-on-chip (SOC) is proposed to be developed using open-source IP cores and fabricated using the MPW facility of ISRO-SCL 180nm technology for the application of secure speech communication. The SOC will implement a vocoder followed by a cryptographic engine for the real-time speech. This developed SOC platform will also have a mechanism (through USB) to interface with a PC for storage and transmission of the encrypted speech. The speech data can be compressed and encrypted using the hardware module and can be sent via existing telephone/VoIP/GSM communication infrastructure. The same hardware module is also used for decrypting and decompressing, and thus original speech data can be retrieved. Standard reference algorithms for voice encoder/decoder, such as code-exited linear predictive (CELP) algorithm and encryption/decryption algorithm such as AES will be employed in this project.