Work Email: jai@ceeri.res.inPersonal Email: jaigopal.pandey@gmail.comMobile: 9983526772EPBX Office: 2394EPBX Residential: 2613BSNL Office: 242359BSNL Residential: BSNL Private: 252613
Dr. Jai Gopal Pandey has received M.Tech. degree in Electronics Design and Technology from U. P. Technical University, Lucknow, India, in 2003. He obtained his Ph.D. degree in Electronics Engineering from Birla Institute of Technology and Science (BITS), Pilani, India in 2015. He is with Council of Scientific and Industrial Research- Central Electronics Engineering Research Institute (CSIR-CEERI), Pilani, Rajasthan-333031, India since 2005. His research interest includes: CMOS VLSI design, High-performance Architecture, SoCs, Embedded System, Cryptography, and FPGA-based design. Dr. Pandey is IETE Fellow, Senior Member of IEEE, and Life Member of Semiconductor Society of India. His ORCID is: http://orcid.org/0000-0001-9937-7438.
Area of Research Interest: VLSI Design, Cryptography, FPGA-based Design
List of Publications: http://orcid.org/0000-0001-9937-7438