BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//CSIR-CEERI, Pilani - EN - ECPv5.16.4//NONSGML v1.0//EN
CALSCALE:GREGORIAN
METHOD:PUBLISH
X-WR-CALNAME:CSIR-CEERI, Pilani - EN
X-ORIGINAL-URL:https://www.ceeri.res.in
X-WR-CALDESC:Events for CSIR-CEERI, Pilani - EN
BEGIN:VTIMEZONE
TZID:Asia/Kolkata
BEGIN:STANDARD
TZOFFSETFROM:+0530
TZOFFSETTO:+0530
TZNAME:IST
DTSTART:20250101T000000
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTART;TZID=Asia/Kolkata:20250303T090000
DTEND;TZID=Asia/Kolkata:20250307T180000
DTSTAMP:20260609T043332
CREATED:20250214T041939Z
LAST-MODIFIED:20250225T144730Z
UID:23280-1740992400-1741370400@www.ceeri.res.in
SUMMARY:Hands-on training programme on Advanced VLSI Design
DESCRIPTION:Entrepreneurship and Skill Development Programme on Advanced VLSI Design\nList of Selected Candidates for MSME’s Entrepreneurship and Skill Development Programme on Advanced VLSI Design\n\nAbout the ProgrammeThis is a hands-on laboratory-oriented programme\, delivered by leading experts from academia\, researchers\, and industry in field of VLSI Design. The training will be delivered using industry standard EDA tools integrated with standard process design kit (PDK). The programme strive to provide students with a comprehensive understanding of the design and implementation of integrated electronic circuits for successful career in IC Design and associated industries. \nTargeted Beneficiaries\nStudents of Pre-final or Final year in B.Tech./MTech./M.Sc./ECE/Electronics/VLSI/Physics) or equivalent\nResearchers and academicians in the field of VLSI\n\nSelection Criteria\nAcademic degree and performance\nReservation as per GoI rules\nIndustrial exposure\nInterview\n\nWho can Apply?\nStudents of Pre-final/Final year in B.Tech./MTech./M.Sc. (ECE/Electronics/VLSI/Physics) or equivalent.\nResearchers and academicians in the field of VLSI design.\nEntrepreneurs working in the similar areas.\nIndustry/MSME/GoI/Private persons.\n\nTerms and Conditions\nSelected candidates shall attend the programme physically.\nAttendance (100%) is mandatory.\nThe course content related\, materials such as hand-outs\, photos\, videos\, and similar other stuffs must not be shared outside.\n\nAPPLY ONLINEscan QR code to register \n \nor apply via the link \nhttps://docs.google.com/forms/d/e/1FAIpQLSfd9gdU3V7K20j_3DA5J56k4tetX07HXa1ZfnhKlw1RqU_2Ww/viewform?usp=dialog \nProgramme Dates: 03-07 March 2025 \nLast Date to Apply: 25 Feb. 2025\, 6:00 PM \nFlyer of EventDownload Flyer \nAbout CSIR-CEERI\, PilaniCentral Electronics Engineering Research Institute (CEERI)\, Pilani\, a constituent laboratory of CSIR. The foundation stone for the establishment of CSIR-CEERI National Laboratory of CSIR was laid on 21st September 1953 by Pt. Jawaharlal Nehru at Pilani. This National Research Laboratory was established to give impetus to research and development of electronics in the country and to make the country self-reliant. \nChips Designed by CSIR-CEERI\, Pilani \nContacts\n\n\n\n\nMr. Pramod Kumar Tanwar\nDr. Jai Gopal Pandey\n\n\n\n\nSr. Principal Scientist & Head PME\nSr. Principal Scientist\n\n\nCSIR-CEERI\, Pilani\nCSIR-CEERI\, Pilani\n\n\npramod@ceeri.res.in\njai@ceeri.res.in\n\n\n01596-252445\n01596-252409
URL:https://www.ceeri.res.in/event/hands-on-training-programme-during-on-advanced-vlsi-design/
LOCATION:CSIR-CEERI\, Pilani\, Central Electronics Engineering Research Institute\, Pilani\, 333031\, India
ORGANIZER;CN="Mr.%20Pramod%20Kumar%20Tanwar":MAILTO:pramod@ceeri.res.in
END:VEVENT
END:VCALENDAR