Integrated Systems

Journals

2020

  • Jai Gopal Pandey, Sanskriti Gupta and Abhijit Karmakar, “A Unified Architecture for AES/PRESENT Ciphers and its Usage in an SoC Environment,” in 11th IEEE Latin American Symposium on Circuits and Systems (LASCAS 2020), pp. 1-4, San Jose, Costa Rica, February 25-28th, 2020.
  • Sajid Khan, Ambika Prasad Shah, Shailesh Singh Chouhan, Sudha Rani, Neha Gupta, Jai Gopal Pandey, Santosh Kumar Vishvakarma, “Utilizing Manufacturing Variations to Design a Tri-State Flip-flop PUF for IoT Security Applications,” Analog Integrated Circuits and Signal Processing, Springer, Vol. 103, Issue 3, pp. 477-492, June 2020.
  • Sajid Khan, Ambika Prasad Shah, Shailesh Singh Chouhan, Neha Gupta, Jai Gopal Pandey, Santosh Vishvakarma,“A symmetric D flip-flop based PUF with improved uniqueness,” Microelectronics Reliability, Elsevier, Jan. 2020.

2019

  • Jai Gopal Pandey, Chhavi Mitharwal and Abhijit Karmakar “An RNS Implementation of the Elliptic Curve Cryptography for IoT Security,” IEEE International Conference on Trust, Privacy and Security in Intelligent Systems and Applications (TPS-ISA), pp. 66-72, 2019, Los Angeles, USA, 12-14 Dec. 2019, IEEE, USA.
  • V. Jeffry Louis and Jai Gopal Pandey, “A Novel Design of SRAM using Memristors at 45 nm Technology,” IEEE 23nd Int’l Symp. on VLSI Design and Test (VDAT), pp. 579-589, 04-06 July 2019, Indore, India; Springer, Singapore.
  • Sajid Khan, Ambika Prasad Shah, Neha Gupta, Shailesh Singh Chouhan, Jai Gopal Pandey, Santosh Vishvakarma “An Ultra-low Power, Reconfigurable, Aging Resilient RO-PUF for IoT Applications” Microelectronics Journal, Vol. 92, pp. 104605, 2019.5.
  • Sajid Khan, Neha Gupta, Gopal Raut, Gunjan Rajput, Jai Gopal Pandey and Santosh Vishvakarma, “An Ultra Low Power AES Architecture for IoT,” IEEE 23nd Int’l Symp. on VLSI Design and Test (VDAT), pp. 334-344, 04-06 July 2019, Indore, India; Springer, Singapore.
  • Sajid Khan, Neha Gupta, Abhinav Vishvakarma, Shailesh Singh Chouhan, Jai Gopal Pandey and Santosh Vishvakarma, “Dual-Edge Triggered Light Weight Implementation of AES for IoT Security,” IEEE 23nd Int’l Symp. on VLSI Design and Test (VDAT), pp. 298-307, 04-06 July 2019, Indore, India; Springer, Singapore.
  • Jai Gopal Pandey, Tarun Goel, Abhijit Karmakar “Hardware Architectures for PRESENT Block Cipher and their FPGA Implementations”, IET Circuits, Devices & Systems, pp. 1-12, May 2019
  • Jai Gopal Pandey and Abhijit Karmakar “Unsupervised image thresholding: hardware architecture and its usage for FPGA-SoC platform”, International Journal of Electronics, Taylor and Francis; March, 2019; 106(3), pp. 455-76

2018

  • Jai Gopal Pandey, Tarun Goel, Mausam Nayak, Chhavi Mitharwal, A. Karmakar and Raj Singh “A High-performance VLSI Architecture of the PRESENT Cipher and its Implementations for SoCs”, 31st IEEE International System-on-chip Conference (SOCC), pp. 96-101, 04-07 September 2018, Arlington, Washington DC, USA
  • Jai Gopal Pandey, Tarun Goel, Mausam Nayak, Chhavi Mitharwal, Sazid Khan, Santosh Kumar Vishvkarma, Abhijit Karmakar and Raj Singh “A VLSI Architecture for the PRESENT Block Cipher with FPGA and ASIC Implementations,” IEEE 22nd Int’l Symp. on VLSI Design and Test (VDAT), Madurai, India, 28 June-30 June 2018.
  • J. G. Pandey, T. Goel, A. Karmakar, A High-performance and Area-efficient VLSI Architecture for the PRESENT Lightweight Cipher, In Proceeding: 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID), Pune, India. Pages, 392-397.

2017

  • J. G. Pandey, T. Goel, A. Karmakar, An Efficient VLSI Architecture for PRESENT Block Cipher and its FPGA Implementation, presented in the 21st International Symposium on VLSI Design and Test (VDAT 2017).
  • Rajul Bansal, Mahendra Kumar Jatav, A. Karmakar, A lifting instruction for performing DWT in LEON3 processor based System-on-Chip, in International Conference on VLSI Design and Test (VDAT-2017), IIT Roorkee, 2017.
  • Rajul Bansal and Abhijit Karmakar, Efficient integration of coprocessor in LEON3 processor pipeline for System-on-Chip design, Microprocessors and Microsystems, Volume 51, pp 56-75, 2017.

2016

  • Jai Gopal Pandey, Aanchal Gurawa, Heena Nehra, and Abhijit Karmakar, “An Efficient VLSI Architecture for Data Encryption Standard and its FPGA implementation” IEEE 2nd Int’l Conf. on VLSI Systems, Architecture, Technology and Applications (VLSI SATA 2016), Bangalore, India, 10-12 January 2016.

2015

  • J. G. Pandey, A. Karmakar, C. Shekhar, and S. Gurunarayanan, An Embedded Framework for Accurate Object Localization using Center of Gravity Measure with Mean Shift Procedure, IEEE 19th International Symposium on VLSI Design and Test, Ahmedabad, India, 26-29 June 2015, pp. 1-6.
  • J. G. Pandey, A. Karmakar, C. Shekhar, and S. Gurunarayanan, Architectures for Embedded Vision Application using FPGA-based Platform User Track of IEEE 28th Int’l Conf. on VLSI Design and 14th Int’l Conf. on Embedded Systems (VLSI Design 2015), Bangalore, India, 3-7 Jan. 2015.

2014

  • J. G. Pandey, A. Karmakar, C. Shekhar, and S. Gurunarayanan, Architectures and algorithms for image and video processing using FPGA-based platform IEEE 18th International Symposium on VLSI Design and Test, Coimbatore, India,16-18 July 2014  pp.1-1.
  • J. G. Pandey, A. Karmakar, A. K. Mishra, C. Shekhar, and S. Gurunarayanan, Implementation of an improved connected component labeling algorithm using FPGA based platform, IEEE International Conference on Signal Processing and Communication (SPCOM), Bangalore, India, 22-25 July 2014 pp. 1-6.
  • J. G. Pandey, A. Karmakar, C. Shekhar, and S. Gurunarayanan, An FPGA-based architecture for kernel-smoothed local histogram computation, International Symposium on Circuits and Systems (ISCAS-2104), Melbourne, Australia, 01-05 June 2014.pp. 2507-2510.
  • J. G. Pandey, A. Karmakar, C. Shekhar, and S. Gurunarayanan ,An FPGA-based novel architecture for the fixed-point binary anti-logarithmic computation IEEE International Conference on Electronic Systems, Signal Processing and Computing Technologies (ICESC), Nagpur, India, 09-11 January 2014, pp. 23-28.
  • J. G. Pandey,A. Karmakar, C. Shekhar, and S. Gurunarayanan, A novel architecture for FPGA implementation of Otsu’s global automatic image thresholding algorithm, IEEE 27th International Conference on VLSI Design and 13th International Conference on Embedded Systems, Mumbai, India, 05-09 January 2014, pp. 300-305.

2013

  • N. Upadhyay and A. Karmakar A perceptually motivated stationary wavelet packet filterbank using improved spectral over-subtraction for enhancement of speech in various noise environments International Journal of Speech Technology, Nov. 2013, vol. 17, no. 2, pp. 1–16.
  • N. Upadhyay and A. Karmakar An improved multi-band spectral subtraction algorithm for enhancing speech in various noise environments, Procedia Engineering, Nov. 2013, vol. 64, no. 1, pp.312–321.
  •  Jai Gopal Pandey, Abhijit Karmakar, Chandra Shekhar, and S. Gurunarayanan, “An FPGA-based fixed-point architecture for binary logarithmic computation,” in Proceedings of 2nd IEEE Int’l Conf. in Image Information Processing (ICIIP-2013), Shimla, India, 09-12 Dec. 2013, pp. 383-388

2012

  • N. Upadhyay and A. Karmakar An auditory perception based improved multi-band spectral subtraction algorithm for enhancement of speech degraded by non-stationary noises IEEE Proceedings of 4th International Conference on Intelligent Human Computer Interaction, Kharagpur, India, Dec. 27–29, 2012  pp. 392-398.
  • N. Upadhyay and A. Karmakar, A perceptually motivated stationary wavelet filter-bank utilizing improved spectral over-subtraction algorithm for enhancing speech in non-stationary environments, IEEE Proceedings of 4th International Conference on Intelligent Human Computer Interaction, Kharagpur, India, Dec. 27–29, 2012,pp. 472–478.
  • Jai Gopal Pandey, Abhijit Karmakar, and Chandra Shekhar, “An embedded architecture for implementation of a video acquisition module of a smart camera system,” in Proceedings of IEEE Int’l Conf. on Devices, Circuits and Systems (ICDCS), Coimbatore, India, 15-16 Mar. 2012, pp. 191-194

2011

  • Pooja Choudhary and Abhijit Karmakar, 2nd International Conference on Computer and Communication Technology (ICCCT), 2011, pp. 550-555, Allahabad, India.
  • Abhijit Karmakar, Arun Kumar, and R. K. Patney. Synthesis of an optimal wavelet based on auditory perception criterion. EURASIP Journal on Advances in Signal Processing 2011.1 (2011): 170927.

2007

  • Abhijit Karmakar, Arun Kumar, and R. K. Patney. Design of optimal wavelet packet trees based on auditory perception criterion. IEEE Signal Processing Letters 14.4 (2007): 240-243.
  • Abhijit Karmakar, Arun Kumar, and R. K. Patney. Design of an optimal two-channel orthogonal filterbank using semidefinite programming. IEEE Signal Processing Letters 14.10 (2007): 692-694.
  • Abhijit Karmakar, Arun Kumar, RK Patney, Design of an Optimal Two-Channel Orthogonal Cyclic Filterbank Using Semidefinite Programming, 2007/12, IEEE Journal of Selected Topics in Signal Processing, Volume 1, Issue 4, Pages 633-640.

2006

  • Abhijit Karmakar, Arun Kumar, and R. K. Patney.  A multiresolution model of auditory excitation pattern and its application to objective evaluation of perceived speech quality. IEEE Transactions on Audio, Speech, and Language Processing 14.6 (2006): 1912-1923.

1998

  • S. Srivastava, SC Bose, Sudhir Kumar, BP Mathur, Arti Noor, Raj Singh, A. Agarwal, AS Mandal, K. Prabhakaran, A. Karmakar, Chandra Shekhar, Evolution of architectural concepts and design methods of microprocessors, 1998. Proceedings of the Eleventh International Conference on VLSI Design, 1998.